Version 0.10.0-3-20170826-1813-dev is a maintenance release; it updates to the latest RISC-V v20170818 release and to the original 1025be3 commit from June 2nd, 2017.

Download

The binary files are available from GitHub Releases.

[2017-09-20 update] It was reported that the RISC-V specific changes have a negative impact on some other targets. Until the problem is identified and a fix released, for non-RISC-V targets please use an older release.

Changes

  • apart from the RISC-V updates, there are no other changes.

Differences from RISC-V release

The following configuration files were added:

  • board/sifive-coreplexip-e31-arty.cfg
  • board/sifive-coreplexip-e51-arty.cfg
  • board/sifive-freedom-e300-hifive1.cfg

Known problems

RISC-V

  • the registers names (x0-x31) displayed in the Registers view are not consistent with the register names in the Disassembly view;
  • the list of register displayed in the Registers view should not include the list of 4096 CSRs

Build notes

The build environment was upgraded to Debian 9.

Binaries

Binaries for Windows, macOS and GNU/Linux are provided. For Windows and macOS, separate installable and plain archives are provided.

Checksums

The SHA-256 hashes for the files are:

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