Version 0.10.0-5-20171110 is a maintenance release; the main change was to patch the RISC-V code to no longer print the 4096 CSRs.

Download

The binary files are available from GitHub Releases.

Changes

  • update to the latest RISC-V 055a70f commit and to the master 7719e96 commit from Aug 10th, 2017
  • patch the monitor reg command to no longer display the RISC-V 4096 CSRs
  • revert the risc-v changes in remote_bitbang.c, since they break the build on mingw-w64

Differences from RISC-V releases

The monitor reg command does not display the 4096 CSRs.

The following configuration files were added:

  • board/sifive-e31arty.cfg
  • board/sifive-e51arty.cfg
  • board/sifive-hifive1.cfg

Known problems

  • none

Build notes

The build environment uses Debian 9 Docker containers.

Binaries

Binaries for Windows, macOS and GNU/Linux are provided. For Windows and macOS, separate installable and plain archives are provided.

Checksums

The SHA-256 hashes for the files are:

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gnu-mcu-eclipse-openocd-0.10.0-5-20171110-1117-win64.zip