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There are two RISC-V toolchains, riscv64-unknown-elf-gcc and riscv32-unknown-elf-gcc (or riscv64-none-elf-gcc and riscv32-none-elf-gcc); you have only one. How can you generate 32 and 64-bit code?

All RISC-V GCC toolchains, if built correctly, are able to generate both 32/64-bit code, based on -march and -mabi. Thus a single version is enough for all use cases.

Why riscv-none-elf-gcc and not riscv-none-eabi-gcc, as Arm uses?

For the moment RISC-V does not define an EABI (Embedded ABI) and uses the same Unix ABI for embedded applications too, thus -eabi- would not be accurate.